1. Field of the Invention
The present invention relates generally to an apparatus and method for controlling data flow in a mobile terminal of a wireless network, and in particular, to a data flow control apparatus and method of a mobile terminal for transmitting data of a high speed communication device, such as a computer device, to a wireless network via a mobile terminal.
2. Description of the Related Art
A wireless network transmits desired transmission data over the air through a specific frequency. With the progress of multimedia technology, the wireless network is developing into a system capable of transmitting high speed packet data. In order to meet various service requirements of users, a terminal of the wireless network is evolving into a complex communication device that can be connected to a general-purpose computer device by wire or wirelessly to perform data exchange, or can function as a wireless modem for accessing the wireless Internet via, for example, a notebook computer.
When a Mobile Terminal (MT) is used as a wireless modem to transmit data output from a high speed communication device (hereinafter a “Terminal Equipment (TE)”) such as a computer device (or Personal Computer (PC)) to the wireless network, the MT is connected to the TE by wire or wirelessly and transmits the data output from the TE to a Base Station (BS) of the wireless network over a reverse link (or uplink).
In order to achieve data transmission from the TE to the BS, there is a need for communication interfaces for connecting the TE to the MT, and the MT to the BS by wire or wirelessly. In the wireless mobile communication standard, an interface for communication between the TE and the MT is defined as an Rm interface, and an interface for communication between the MT and the BS is defined as a Um interface.
In wireless communication technology, the Rm interface supports a data rate of several hundreds of Mbps according to various communication standards such as Universal Serial Bus (USB) Version 2.0, Fast Ethernet, and the like. The Um interface supports a data rate of a maximum of 1.8 Mbps in Evolution—Data Only (EV-DO), for a synchronous terminal, and supports a data rate of a maximum of 5.8 Mbps in High Speed Uplink Packet Access (HSUPA), for an asynchronous terminal. That is, the Um interface, compared with the Rm interface, supports a lower data rate.
Therefore, when the processed data from the TE is transmitted to a wireless network via the MT, a data transmission error may occur due to a rate difference between the Rm interface and the Um interface. The data transmission error occurs because as the data received via the higher-rate Rm interface on a burst basis experiences data bottleneck in the lower-rate Um interface, buffer overflow or buffer underrun may occur instantaneously. Therefore, in order to minimize the occurrence of the data transmission error due to the rate difference between the Rm interface and the Um interface, there is a need for a data flow control scheme capable of stably controlling data flow between the Rm interface and the Um interface.
A description will now be made of a data flow control apparatus of a conventional mobile terminal using the Rm interface and the Um interface, with reference to FIG. 1.
Referring to FIG. 1, a data flow control apparatus 100 included in an MT includes an Rm interface unit 110 as a communication interface between a TE 101 and the MT and a Um interface unit 170 as a communication interface between the MT and a BS 102, to perform reverse transmission from the TE 101 to the BS 102.
In reverse communication, the Rm interface unit 110 is an interface for receiving data from the TE 101. The Rm interface unit 110 includes therein a buffer for temporarily storing data received from the TE 101, and performs basic flow control based on a watermark. An Operating System (OS) device driver 130 reads data delivered from the Rm interface unit 110, and stores it in a buffer in the MT. The OS device driver 130 can have access to upper layer modules via an OS Application Program Interface (API). A packet processor 150 performs a process of converting the data that the OS device driver 130 has copied in byte stream format, into a packet format. The Um interface unit 170 is an interface for transmitting the data in the packet format received from the packet processor 150 to the BS 102. A controller 190 controls the overall operation of communication and additional functions achieved in the data flow control apparatus 100, and particularly controls the flow of data transmitted from the Rm interface unit 110 via the OS device driver 130, the packet processor 150 and the Um interface unit 170.
FIG. 2 illustrates a data transmission process in the data flow control apparatus 100 shown in FIG. 1. In FIGS. 1 and 2, the same or similar elements are denoted by the same reference numerals even though they are depicted in different drawings.
Referring to FIG. 2, an Rm interface unit 110, including a First-In-First-Out (FIFO) buffer 111, buffers the data received from a TE 101 in the FIFO buffer 111 to temporarily store it in a byte stream. If the amount of data stored in the FIFO buffer 111 is greater than or equal to a reference amount, the Rm interface unit 110 sends an interrupt signal to an OS device driver 130.
The OS device driver 130, paged through the interrupt signal, reads data from the FIFO buffer 111, and stores the read data in a byte stream buffer 131 in the byte stream format. The byte stream buffer 131 should have a buffer capacity corresponding to the maximum amount of packet, expected to prevent a loss of a data packet received from the TE 101. In addition, after storing the data in the byte stream buffer 131, the OS device driver 130 sends an event signal indicating the data storing to a packet processor 150, which is its upper layer. In this process, the OS device driver 130 performs a Clear-To-Send (CTS) control that restricts data transmission from the TE 101 to prevent a data loss when the amount of data stored in the byte stream buffer 131 is greater than or equal to a reference amount.
The packet processor 150 copies as much data as needed in the byte stream buffer 131 using an OS API. The copied byte stream-format data is converted into packet-format data, and then added to a packet buffer field in a packet buffer queue 153 allocated in a packet buffer pool 151. That is, every time the copied data is converted into packet-format data, the packet processor 150 stores the corresponding packet in its own packet buffer queue 153 for efficient packet processing.
A Um interface unit 170, including a byte stream buffer 171, stores the copied data from the packet processor 150 in the byte stream buffer 171, converts the data into a frame format suitable for the wireless network transmission standard, and then transmits the frame-format data to a BS 102.
In the data flow control apparatus 100 of FIG. 2, in order to buffer the packet-format data and the byte stream-format data independently, the OS device driver 130 and the Um interface unit 170 include byte stream buffers 131 and 171, respectively, and the packet processor 150 includes the packet buffer pool 151 and the packet buffer queue 153. Therefore, in the conventional data flow control apparatus 100, as the modules participating in the reverse transmission path from the Rm interface unit 110 to the Um interface unit 170 use different buffer structures, consistent and correct flow control is hard to implement.
Further, in the conventional data flow control apparatus 100, the controller 190 needs the interfaces capable of individually controlling the modules that use the different buffer structures. That is, when a buffer-full state occurs in the Um interface unit 170, the controller 190 sends an interrupt request signal for data transmission to the TE 101, and the interrupt request signal is delivered to the Rm interface unit 110 in degrees, so that data transmission interrupt is performed according to CTS control.
However, because the data flow control process performed in the controller 190 is performed through task scheduling between the modules of the data flow control apparatus 100, a time difference occurs when the buffer-full state of the Um interface unit 170 is reflected in the Rm interface unit 110, so the data flow control cannot be achieved at the desired time in real time. Therefore, the conventional data flow control apparatus 100 accumulates an unnecessarily large amount of data in each protocol stack, causing retransmission in the upper layer and thus causing performance degradation.
In addition, the time difference occurring in the conventional flow control process delays a data-receivable state in the Rm interface unit 110 even when the FIFO buffer 111 in the Rm interface unit 110 is emptied, thereby causing buffer underrun in which data transmission to the BS 102 is temporarily interrupted.
In the conventional data flow control apparatus, because flow control is performed without the information indicating the amount of packet data accumulated in the upper layer as described above, there is a possibility that buffer overflow and underrun will occur in the Um interface unit, and due to the difficulty in expecting that possibility, there is a burden of securing the more-than-necessary buffer capacity. However, the increase in memory capacity of a terminal can be a direct cause of decreasing the price competitiveness of the terminal, and the overflow and the underrun may cause performance degradation in packet transmission. In addition, because the conventional technique, in which different modules manage buffers having different structures, should infringe S/W (software) independence of each module in order to share buffer information of other modules, it is hard to measure residual buffer capacity of the data accumulated in the entire reverse link in real time and to control data flow. Alternatively, it is also possible to perform the flow control between the modules through feedback messages. In this case, however, for buffer control, it is necessary to match synchronization in real time.
That is, in the conventional data flow control apparatus, because flow control is distributed in each module and the flow control is not achieved at an appropriate time, there is a high possibility that a decrease in data rate and a change in transmission may occur. Therefore, complex processing is needed to solve these problems. In addition, because there is a possibility that a processing load of the controller may increase due to the buffer copy (i.e. data copy) performed in a process of delivering the packet stored in the Rm interface unit to the upper layer and the increase in the processing load may cause performance degradation in high speed data communication to be upgraded later, there is a need for a solution for these problems.